The present invention relates generally to semiconductor design technology, and more particularly to a method and apparatus for synchronization of the multiple input/output of a semiconductor device.
Speed and timing constraints have always been important considerations in designing electronic systems. Most system designs must match the timing requirements of all the components used, yet still be optimized for high speed. As a result, many integrated circuits, or "chips," utilize a synchronous design. A synchronous chip is one in which components of the chip are connected to a common system clock. Synchronous chips also have latches or registers connected to inputs and outputs, all on a single monolithic chip. For example, U.S. Pat. No. 5,426,333 to Maeda describes a synchronous dynamic random access memory chip. Synchronous chips provide many benefits to system designers, such as fewer external logic chips and high speed operation. However, synchronous chips also present several design difficulties for chip designers.
One such design difficulty is the routing of the clock signal throughout the chip. Due to the effects of transmission line impedance, the clock signal as seen on one side of the chip is typically delayed from the same clock signal, as seen on the opposite side of the chip. This problem is exacerbated by increased chip size and an increased number of input/output ("I/O") ports. For example, a 256 mega-bit ("Mbit") dynamic random access memory ("DRAM") is very large in size, and can have as many as 16 I/O ports on a single chip.